Universität Heidelberg IWR HITS SPPEXA

Fast high order DG methods for future architectures

July 3 - 5, 2017

Heidelberg

The joint workshop of the EXA-DUNE, EXAMAG and ExaDG projects, being part of the DFG Priority Programme Software for Exascale Computing (SPPEXA), will take place at the Mathematikon in Heidelberg, Germany. The event will be hosted collaboratively by the Heidelberg Institute for Theoretical Studies (HITS) and Heidelberg University's Interdisciplinary Center for Scientific Computing (IWR).

SPPEXA addresses fundamental research on the various aspects of HPC software, which is particularly urgent against the background that we are currently entering the era of ubiquitous massive parallelism. Exploiting this massive parallelism on future computer architectures will allow for extreme computing up to exascale, i.e. computations achieving 1018 floating point operations per second and beyond. Mastering the various challenges on the way up to exascale computing demands efficient mathematical methods and fast algorithms, which are fulfilling the paradigm shift to highly parallel processing.

The workshop provides a discussion venue for mathematical and algorithmic problems arising when implementing fast, parallel solvers for high-order DG discretizations of PDE problems. Key aspects are

  1. considering how to exploit tensorial structures to reduce the complexity of local cell and face integral evaluation within a matrix-free based code,
  2. using algebraic multigrid methods in a computationally intensive framework,
  3. an implementation of efficient cell- and patch-based smoothers for geometric multigrid methods applicable in a massively parallel environment,
  4. data locality and
  5. heterogeneous parallelism, e.g. as when computing boundary and volume integrals simultaneously.

In particular, the algorithms above and mathematical models are discussed with regard to their enhancement of performance and scalability by employing hybrid parallelization techniques, namely multithreading and message passing, combined with low-level optimizations that make full use of vector instructions and device accelerators.

Invited Speakers

Organizers

Contact

Prof. Dr. G. Kanschat, IWR, Universität Heidelberg, Im Neuenheimer Feld 205, 69120 Heidelberg
Valid XHTML 1.1 Valid CSS!